3.3V Single-Piece 4Mb Nonvolatile SRAM
with Clock
Write Cycle 1
t WC
ADDRESSES
V IH
V IL
V IH
V IL
V IH
V IL
t AW
CE
OR
CS
V IL
t WP
V IL
t WR1
WE
V IH
V IL
V IL
V IH
D OUT
t ODW
HIGH
IMPEDANCE
t OEW
D IN
V IH
V IL
t DS
DATA IN STABLE
t DH1
V IH
V IL
(SEE NOTES 2, 3, 4, 6, 10 – 13.)
Write Cycle 2
t WC
ADDRESSES
V IH
V IL
t AW
t WP
t WR2
V IH
V IL
V IH
V IL
CE
OR
CS
V IH
V IL
V IL
V IL
V IH
V IH
WE
D OUT
t COE
V IL
t ODW
V IL
D IN
(SEE NOTES 2, 3, 5, 6, 10 – 13.)
V IH
V IL
t DS
DATA IN STABLE
t DH2
V IH
V IL
6
_____________________________________________________________________
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